1. Field of the Invention
This invention relates to a semiconductor device, a method for manufacturing and a method for driving the same. More particularly, the invention relates to a memory integrally providing on the same chip a non-volatile memory (mask ROM) and a dynamic semiconductor memory (DRAM).
2. Description of the Prior Art
As a read only non-volatile memory, mask ROMs which are programmed with data during a manufacturing process are conventionally known. Mask ROMs of a contact hole programming type, as shown in FIG. 21, store data depending on whether or not a drain region D of a transistor T constituting each memory device is connected to bit line Y or Y1. In other words, data is written into the semiconductor device depending on whether a contact hole is opened which connects the bit line to the drain region of the transistor in the manufacturing process of semiconductor devices.
On the other hand, a dynamic semiconductor memory which can be programmed by users is also known.
in view of the user's convenience it is desirable to use both of the above two memories. However, a problem has arisen in that it is difficult to manufacture the read only non-volatile memory and the dynamic semiconductor memory on the same chip in the same manufacturing process because the two memories are different in structure.
For example, Japanese Unexamined Patent Publication No. SHO 56(1981)-27958 and Japanese Unexamined Patent Publication No. HEI 5(1993)-120889 disclose semiconductor devices in which a ROM and a RAM are formed on the same chip. Japanese Unexamined Patent Publication No. SHO 56(1981)-27958 describes a cell of a planar type as shown in FIG. 22 in which one end of the capacitor in the cell is connected to a transistor while the other end of the capacitor is connected to GND. In other words, FIG. 22 describes a semiconductor device that is programmed depending on whether both ends of the capacitor are not connected to each other as seen in cell Mbp or are short-circuited as seen in cell Map. However, for example, when a word line Xop is selected in the semiconductor device (and most of the memory cells connected to the word line Xop are given as cells in which both ends of the capacitor are short-circuited as seen in the cell Mbp), there arises a problem that a plate electrode constituting a capacitor in cell Mbp might be short-circuited with a bit line which works as a data line, which varies potential of the plate electrode and generates a noise. The variation in the potential of the plate electrode is transmitted to the plate electrode of cell Map, thereby affecting the bit line connected to cell Map which might induce an error in operation.
Moreover, Japanese Unexamined Patent Publication No. HEI 5(1993)-120889 discloses a semiconductor device having a stack cell. A capacitor of RAM in this semiconductor device is connected to an impurity region on one side of a transistor, and has a node electrode being connected to the definite potential. The capacitor of ROM in this semiconductor device is connected to the impurity region on one side of a transistor, and has a plate electrode which is either connected to a definite potential or provided to be opened. However, for example when a certain word line is selected in this semiconductor device (and most of the memory cells connected to the word line have a capacitor having a node electrode connected to the definite potential as described above), there arises a problem that the node electrode connected to the definite potential might be short-circuited with the bit line which works as the data line. In such a case, the definite potential of the node electrode varies and even the potential of the plate electrode is varied via a capacitance between the node and the plate electrodes. Furthermore, the variation in the potential at the plate electrode affects a cell having an opened plate electrode and appears in the data line to which the cell is connected, thereby causing an error in operation.